Problem

The traditional CMOS technology used for designing adders was not meeting their requirements of low power consumption and high speed.

My moto is to design an adder that could perform arithmetic operations with minimal power consumption and high speed while using the QCA technology. Me and my project mates had to come up with a solution that could meet their requirements and outperform the traditional CMOS technology.

Learn more about our solution here.

Solution

Our team of college students analyzed the requirements and came up with a novel design for the adder using QCA technology. We used a combination of complementary logic gates and majority gates to implement the adder circuit.

The complementary logic gates helped in reducing the power consumption by eliminating the static power dissipation. The majority gates were used to reduce the delay in carry propagation, which increased the speed of operation. We also implemented a clock gating technique to further reduce power consumption when the circuit was idle.

Designed the complementary logic gates and majority gates for the adder circuit
Implemented the clock gating technique to reduce power consumption
Verification Engineer
Developed testbenches to verify the functionality of the adder circuit
Analyzed simulation results and provided feedback for improvements

Efficient Adder Design with QCA Technology